TIMER_SEL=IMO, TIMER_HF0_DIV=NO_DIV
Timer Clock Control Register
| TIMER_SEL | Select source for TIMERCLK. The output of this mux can be further divided using TIMER_DIV. 0 (IMO): IMO - Internal Main Oscillator 1 (HF0_DIV): Select the output of the predivider configured by TIMER_HF0_DIV. |
| TIMER_HF0_DIV | Predivider used when HF0_DIV is selected in TIMER_SEL. If HFCLK0 frequency is less than 100MHz and has approximately 50 percent duty cycle, then no division is required (NO_DIV). Otherwise, select a divide ratio of 2, 4, or 8 before selected HF0_DIV as the timer clock. 0 (NO_DIV): Transparent mode, feed through selected clock source w/o dividing or correcting duty cycle. 1 (DIV_BY_2): Divide HFCLK0 by 2. 2 (DIV_BY_4): Divide HFCLK0 by 4. 3 (DIV_BY_8): Divide HFCLK0 by 8. |
| TIMER_DIV | Divide selected timer clock source by (1+TIMER_DIV). The output of this divider is TIMERCLK Allows for integer divisions in the range [1, 256]. Do not change this setting while the timer is enabled. |
| ENABLE | Enable for TIMERCLK. 0: TIMERCLK is off 1: TIMERCLK is enabled |